EM484M3244VBA Datasheet, PDF (15/17 Pages) Eorex Corporation – 128Mb (1M×4Bank×32) Synchronous DRAM

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EM484M3244VBA
4. Operative Command Table (Continued) ^{(Note 7)}
Current
State
/CS /R /C /W
Addr.
Command
Action
H XX X
X
DESL
Nop → Enter row active after t_DPL
L HH H
X
NOP
Nop → Enter row active after t_DPL
L HH L
X
BST
Nop → Enter row active after t_DPL
L H L H BA/CA/A10 READ/READA Start read, Determine AP
Write
L
Recovering
L
H L L BA/CA/A10
L H H BA/RA
WRIT/WRITA
ACT
New write, Determine AP ^{(Note 14)}
ILLEGAL ^{(Note 9)}
L L H L BA, A10
PRE/PALL
ILLEGAL ^{(Note 9)}
L LLH
X
REF/SELF ILLEGAL
L L L L Op-Code
MRS
ILLEGAL
H XX X
X
DESL
Nop → Enter pre-charge after t_DPL
L HH H
X
NOP
Nop → Enter pre-charge after t_DPL
Write
L HH L
X
BST
Nop → Enter pre-charge after t_DPL
L H L H BA/CA/A10 READ/READA ILLEGAL ^{(Note 9, 14)}
Recovering _{L H L L BA/CA/A10 WRIT/WRITA ILLEGAL} ^{(Note 9)}
with AP
L LHH
BA/RA
ACT
ILLEGAL ^{(Note 9)}
L L H L BA, A10
PRE/PALL ILLEGAL
L LLH
X
REF/SELF ILLEGAL
L L L L Op-Code
MRS
ILLEGAL
H XX X
X
L HH X
X
Refreshing _{L H L X}
X
DESL
NOP/BST
READ/WRIT
Nop → Enter idle after t_RC
Nop → Enter idle after t_RC
ILLEGAL
L LHX
X
ACT/PRE/PALL ILLEGAL
L LLX
X
REF/SELF/MRS ILLEGAL
H XX X
X
DESL
Nop
Mode
Register
L HH H
L HH L
Accessing ^{L H L X}
L LXX
X
NOP
Nop
X
BST
ILLEGAL
X
READ/WRIT ILLEGAL
X
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle.
Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
Note 9: Illegal to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
Note 11: Illegal if t_RCD is not satisfied.
Note 12: Illegal if t_RAS is not satisfied.
Note 13: Must satisfy burst interrupt condition.
Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 15: Must mask preceding data which don't satisfy t_DPL.
Note 16: Illegal if t_RRD is not satisfied.
Jul. 2006
15/17
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