EM48AM3284LBB_15 Datasheet, PDF (10/22 Pages) Eorex Corporation – Mobile Synchronous DRAM

EM48AM3284LBB
AC Operating Test Characteristics (Continued)
(V_DD=1.7~1.95V, T_A=-25°C ~85°C for extended)
Symbol
Parameter
ACTIVE to ACTIVE Command
t_RC
Period ^{(Note 6)}
-6
-7.5
Units
Min. Max. Min. Max.
90
90
ns
ACTIVE to PRECHARGE
t_{RAS Command Period (Note 6)}
PRECHARGE to ACTIVE
t_RP
Command Period ^{(Note 6)}
42 100k 45 100k ns
18
22.5
ns
ACTIVE to READ/WRITE Delay
t_RCD
Time ^{(Note 6)}
18
22.5
ns
ACTIVE(one) to ACTIVE(another)
t_RRD
Command ^{(Note 6)}
12
15
ns
t_CCD
READ/WRITE Command to
READ/WRITE Command
1
1
CLK
t_DPL
Date-in to PRECHARGE
Command
2
2
CLK
t_BDL Date-in to BURST Stop Command
1
1
CLK
Data-out to High
t_ROH Impedance from
CL=3 3
PRECHARGE Command
3
CLK
t_REF Refresh Time (8,192 cycle)
64
64 Ms
t_DAL Data-in to ACTIVE command
33
37.5
ns
* All voltages referenced to V_SS.
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of
the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all V_DD and V_DDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed V_DD+0.3V on any of the input pins or V_DD supplies. (CLK signal started at same time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge
command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held
high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command
must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required,
and these may be done before or after programming the Mode Register.
Nov. 2010
10/22
www.eorex.com