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EM48AM1684LBA Datasheet, PDF (1/17 Pages) Eorex Corporation – 256Mb (4M×4Bank×16) Synchronous DRAM
eorex
EM48AM1684LBA
256Mb (4M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• VDD/VDDQ= 1.8V +/- 0.15V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
Description
The EM48AM1684LBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 1.8V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVCMOS.
Available packages:
P-VFBGA 54B 12mm x 8mm x 1mm.
Ordering Information
Part No
Organization Max. Freq
Package
Grade Pb
EM48AM1684LBA-75F
16M X 16 133MHz @CL3 P-VFBGA -54B II Commercial Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
www.eorex.com
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