EM48AM1644VBC Datasheet, PDF (1/19 Pages) Eorex Corporation – 256Mb (4M×4Bank×16) Synchronous DRAM

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Preliminary
EM48AM1644VBC
256Mb (4M×4Bank×16) Synchronous DRAM
Features
• 2 x 4 banks x 2 Mbit x 16 organisation ( Two
128MBit chips stacked in multi-chip package)
• Fully Synchronous to Positive Clock Edge
• Single 2.7V ~ 3.6V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length –1/2/4/8/ full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 4/8)
• Burst Read with Single-bit Write Operation
• Deep Power Down Mode.
• Auto Refresh and Self Refresh
• Special Function Support.
– PASR (Partial Array Self Refresh)
– Auto TCSR (Temperature Compensated Self
Refresh)
• Programmable Driver Strength Control
– Full Strength or 1/2, 1/4 of Full Strength
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM48AM1684VBC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2 x 4 banks x 2 Mbit by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.0/3.3V low
power memory system. It also provides auto
refresh with power saving / down mode. All inputs
and outputs voltage levels are compatible with
LVCMOS.
Available packages:TFBGA 54B 12mm x 8mm.
Ordering Information
Part No
Organization Max. Freq
EM48AM1644VBC-75F 2 die X 8M X 16 133MHz @CL3
EM48AM1644VBC-75FE 2 die X 8M X 16 133MHz @CL3
Package
Grade Pb
TFBGA -54B Commercial Free
TFBGA -54B Extend temp. Free
May. 2007
* EOREX reserves the right to change products or specification without notice.
www.eorex.com
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