EM488M3244VBC Datasheet, PDF (1/19 Pages) Eorex Corporation – 256Mb (2M×4Bank×32) Synchronous DRAM

eorex
Preliminary
EM488M3244VBC
256Mb (2M×4Bank×32) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 2.7V ~ 3.6V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• Deep Power Down Mode.
• Auto Refresh and Self Refresh
• Special Function Support.
– PASR (Partial Array Self Refresh)
– Auto TCSR (Temperature Compensated Self
Refresh)
• Programmable Driver Strength Control
– Full Strength or 1/2, 1/4 of Full Strength
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M3244VBC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVCMOS.
Available packages: BGA-90B (13mmx8mm).
Ordering Information
Part No
EM488M3244VBC-75F
EM488M3244VBC-75FE
Organization
8M X 32
8M X 32
Max. Freq
133MHz @CL3
133MHz @CL3
Package
BGA-90B
BGA-90B
Grade Pb
Commercial Free
Extend temp. Free
* EOREX reserves the right to change products or specification without notice.
May. 2007
www.eorex.com
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