EM488M1644VBB Datasheet, PDF (1/17 Pages) Eorex Corporation – 128Mb (2M×4Bank×16) Synchronous DRAM

eorex
EM488M1644VBB
128Mb (2M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 2.75V ~ 3.6V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Ordering Information
Description
The EM488M1644VBB is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TFBGA-54B(8mmx8mm).
Part No
Organization Max. Freq
EM488M1644VBB-75F
8M X 16
133MHz @CL3
EM488M1644VBB-7F
8M X 16
143MHz @CL3
EM488M1644VBB-75FE
8M X 16
133MHz @CL3
EM488M1644VBB-7FE
8M X 16
143MHz @CL3
EM488M1644VBB-75
8M X 16
133MHz @CL3
EM488M1644VBB-7
8M X 16
143MHz @CL3
Package
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
Grade
Commercial
Commercial
Extend temp
Extend temp
Special request
Special request
Pb
Free
Free
Free
Free
Pb
Pb
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
www.eorex.com
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