EM488M1644LBC Datasheet, PDF (1/17 Pages) Eorex Corporation – 128Mb (2M×4Bank×16) Synchronous DRAM

eorex
EM488M1644LBC
128Mb (2M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 1.7V-1.95V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M1644LBC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 1.8V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: FBGA 54B.
Ordering Information
Part No
EM488M1644LBC-6F
Organization Max. Freq
8M X 16
166MHz @CL3
Package
54B FBGA
Grade Pb
Commercial Free
* EOREX reserves the right to change products or specification without notice.
Jan. 2013
www.eorex.com
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