EM42BM1684LBB Datasheet, PDF (1/20 Pages) Eorex Corporation – 512Mb (8M×4Bank×16) Double DATA RATE SDRAM

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Preliminary EM42BM1684LBB
Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• 1.8V ±0.1V VDD/VDDQ
• 1.8V LV-COMS compatible I/O
• Burst Length (B/L) of 2, 4, 8, 16
• 3 Clock read latency (CL3)
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• No DLL;CK to DQS is not synchronized
• Deep power down mode
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh
(TCSR) by built-in temperature sensor
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
512Mb (8M×4Bank×16)
Double DATA RATE SDRAM
Description
The EM42BM1684LBB is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 536,870,912 bits which
organized as 8Meg words x 4 banks by 16 bits.
The 512Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:FBGA-60B(11.5mmx10mm).
Ordering Information
Part No
Organization
Max. Freq
Package Grade Pb
EM42BM1684LBB-75F
32M X 16 133MHz/DDR266 @CL3 BGA-60B Commercial. Free
EM42BM1684LBB-75FE 32M X 16 133MHz/DDR266 @CL3 BGA-60B Extend Temp. Free
Jul. 2006
* EOREX reserves the right to change products or specification without notice.
www.eorex.com
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