EN25F10A Datasheet, PDF (53/62 Pages) Eon Silicon Solution Inc. – 1 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25F10A
Table 14. 104 MHz AC Characteristics
(T_a = - 40°C to 85°C; V_CC = 2.7-3.6V)
Symbol Alt
Parameter
Serial Clock Frequency for:
FAST_READ, PP, QPP, SE, HBE, BE, DP, RES,
F_R
f_C
WREN, WRDI, WRSR, RDSR
Serial Clock Frequency for:
RDID, Dual Output Fast Read and Quad I/O Fast
Read
f_R
t_CH ¹
t_CL1
t_CLCH2
t_CHCL ²
t_SLCH
Serial Clock Frequency for READ
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
t_{CSS CS# Active Setup Time (Relative to CLK)}
t_CHSH
CS# Active Hold Time (Relative to CLK)
t_SHCH
CS# Not Active Setup Time (Relative to CLK)
t_CHSL
CS# Not Active Hold Time (Relative to CLK)
t_SHSL
t_CSH
CS# High Time for read
CS# High Time for program/erase
t_SHQZ ²
t_CLQX
t_{DIS Output Disable Time}
t_{HO Output Hold Time}
t_DVCH
t_{DSU Data In Setup Time}
t_CHDX
t_{DH Data In Hold Time}
t_HLCH
HOLD# Low Setup Time ( relative to CLK )
t_HHCH
HOLD# High Setup Time ( relative to CLK )
t_CHHH
HOLD# Low Hold Time ( relative to CLK )
t_CHHL
t_HLQZ ²
t_HHQX ²
t_CLQV
t_WHSL3
t_SHWL3
t_DP ²
t_RES1 ²
t_RES2 ²
t_W
HOLD# High Hold Time ( relative to CLK )
t_{HZ HOLD# Low to High-Z Output}
t_{LZ HOLD# High to Low-Z Output}
t_V
Output Valid from CLK for 30 pF
Output Valid from CLK for 15 pF
Write Protect Setup Time before CS# Low
Write Protect Hold Time after CS# High
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
t_PP
Page Programming Time
t_SE
Sector Erase Time
t_BE
32KB Block Erase Time
64KB Block Erase Time
t_CE
Chip Erase Time
Min
D.C.
D.C.
D.C.
4
4
0.1
0.1
5
5
5
5
7
30
-
0
2
5
5
5
5
5
-
20
100
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
0.7
0.03
0.1
0.2
0.4
Max
Unit
104
MHz
104
MHz
50
MHz
-
ns
-
ns
-
V / ns
-
V / ns
-
ns
-
ns
-
ns
-
ns
-
ns
ns
6
ns
-
ns
-
ns
-
ns
ns
ns
ns
ns
6
ns
6
ns
8
6
ns
-
ns
-
ns
3
µs
3
µs
1.8
µs
15
ms
3
ms
0.2
s
0.5
1
s
2
s
t_SR
Software Reset ^{WIP = write operation}
-
-
28
µs
Latency
WIP = not in write operation
-
-
0
µs
Note: 1. t_CH + t_CL must be greater than or equal to 1/ f_C
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
This Data Sheet may be revised by subsequent versions
53
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/11/12
www.eonssi.com