EN25F05_1 Datasheet, PDF (5/32 Pages) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

MEMORY ORGANIZATION
The memory is organized as:
65,536 bytes
Uniform Sector Architecture
2 blocks of 32-Kbyte
16 sectors of 4-Kbyte
256 pages (256 bytes each)
EN25F05
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
1
0
Sector
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address range
00F000h
00FFFFh
00E000h
00EFFFh
00D000h
00DFFFh
00C000h
00CFFFh
00B000h
00BFFFh
00A000h
00AFFFh
009000h
009FFFh
008000h
008FFFh
007000h
007FFFh
006000h
006FFFh
005000h
005FFFh
004000h
004FFFh
003000h
003FFFh
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
OPERATING FEATURES
SPI Modes
The EN25F05 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in
Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the
CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2010/04/15
www.eonssi.com