EN25S20A Datasheet, PDF (31/65 Pages) Eon Silicon Solution Inc. – 2 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

EN25S20A
Read Burst (0Ch)
To execute a Read Burst operation (Figure 20) the host drivers CS# low, and sends the Read Burst
command cycle (0Ch), followed by three address cycles and one dummy cycles (8 clocks).
After the dummy cycle, the device outputs data on the falling edge of the CLK signal starting from the
specific address location. The data output stream is continuous through all addresses until terminated
by a low-to high transition of CS# signal.
During Read Burst, the internal address point automatically increments until the last byte of the burst
reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the bust length,
see Table 9. For example, if the burst length is 8 bytes, and the start address is 06h, the burst
sequence should be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05, 06, etc. The pattern would repeat until the
command was terminated by pulling CS# as high status.
The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Table 9. Burst Address Range
Burst length
Burst wrap (A[7:A0]) address range
8 Bytes ( default)
00-07h, 08-0Fh, 10-17h, 18-1Fh...
16 Bytes
00-0Fh, 10-1Fh, 20-2Fh, 30-3Fh...
32 Bytes
00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...
64 Bytes
00-3Fh, 40-7Fh, 80-BFh, C0-FFh
CS#
CLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
DI
DO
Command
0Ch
3 Address bytes
(24 clocks)
Dummy Byte
A23 A22 A21
*
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
*
CS#
CLK
* ^{= MSB}
39 40 41 42 43 44 45 46 47 48 49
54 55
n n+1
Data Byte 1
Data Byte 2
Data Byte n
DI
D0
DO
CS#
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
*
*
D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7
*
*
CLK
DI
DO
Data Byte 1
Data Byte 2
Data Byte n
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
*
*
D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7
*
*
Figure 20. Read Burst Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
31
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2014/01/16
www.eonssi.com