EN25Q40A Datasheet, PDF (19/64 Pages) Eon Silicon Solution Inc. – 4 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q40A
Figure 10.1 Read Status Register Instruction Sequence in QPI Mode
Table 6. Status Register Bit Locations
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Status
Register
Protect
OTP_LOCK
bit
(note 1)
WPDIS
(WP# disable)
BP3
(Block
Protected bits)
BP2
BP1
BP0
(Block
(Block
(Block
Protected bits) Protected bits) Protected bits)
WEL
(Write Enable
Latch)
WIP
(Write In
Progress bit)
(Note 3)
1 = status 1 = OTP
register write sector is
disable
protected
1 = WP#
disable
0 = WP#
enable
(note 2)
(note 2)
(note 2)
(note 2)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
Non-volatile bit
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits
are 0.
This Data Sheet may be revised by subsequent versions
19
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. F, Issue Date: 2014/04/02
www.eonssi.com