EN25F80 Datasheet, PDF (16/33 Pages) Eon Silicon Solution Inc. – 8 Mbit Serial Flash Memory with 4Kbytes Uniform Sector

EN25F80
is t_SE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 3) is not executed.
Block Erase (BE) (D8h/52h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be accepted,
a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see Table 2) is a
valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 13.. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is t_SE) is
initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP2, BP1, BP0)
bits (see Table 3) is not executed.
This Data Sheet may be revised by subsequent versions ₁₆ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2007/05/16