EN25B32 Datasheet, PDF (11/38 Pages) Eon Silicon Solution Inc. – 32 Mbit Serial Flash Memory with Boot and Parameter Sectors

EN25B32
Table 3a. Protected Area Sizes- Bottom Boot Sector Organization
Status Register
Content
BP2 BP1 BP0
Bit Bit Bit
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Memory Content
Protect Sectors
All
Sector 0 to 35
Sector 0 to 4
Sector 0 to 3
Sector 0 to 2
Sector 0 to 1
Sector 0
None
Addresses
000000h-3FFFFFh
000000h-1FFFFFh
000000h-00FFFFh
000000h-007FFFh
000000h-003FFFh
000000h-001FFFh
000000h-000FFFh
None
Density(KB)
Portion
4096KB
2048KB
64KB
32KB
16KB
8KB
4KB
None
All
Lower 1/2
Lower 1/64
Lower 1/128
Lower 1/256
Lower 1/512
Lower 1/1024
None
Table 3b. Protected Area Sizes- Top Boot Sector Organization
Status Register
Content
BP2 BP1 BP0
Bit Bit Bit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protect Sectors
None
Sector 67
Sector 66 to 67
Sector 65 to 67
Sector 64 to 67
Sector 63 to 67
Sector 32 to 67
All
Memory Content
Addresses
Density(KB)
None
3FF000h-3FFFFFh
3FE000h-3FFFFFh
3FC000h-3FFFFFh
3F8000h-3FFFFFh
3F0000h-3FFFFFh
200000h-3FFFFFh
000000h-3FFFFFh
None
4KB
8KB
16KB
32KB
64KB
2048KB
4096KB
Portion
None
Upper 1/1024
Upper 1/512
Upper 1/256
Upper 1/128
Upper 1/64
Upper 1/2
All
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition
starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)
being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with
Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and
Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment
of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the
internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)
High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold
condition.
This Data Sheet may be revised by subsequent versions ₁₁ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/06/21