EV1380QI Datasheet, PDF (6/16 Pages) Enpirion, Inc. – 8a synchronous highly integrated dc-dc

EV1380 Datasheet Rev A
PARAMETER
V_POK Logic high level
POK Current Sink
Capability
VTT Tracking VDDQ
Enable Pin Current
Logic Low Threshold
Logic High Threshold
S_OUT Low Level
S_OUT High Level
M/S Pin Logic Low
Threshold
M/S Pin Logic High
Threshold
M/S Pin Input Current
Current Balance
SYMBOL
TEST CONDITIONS
3.07V ≤ AVIN ≤ 3.53V
VDDQ – 2*VTT
I_EN
V_B-LOW
V_B-HIGH
V_{S_OUT_LOW}
V_{S_OUT_HIGH}
VDDQ > 1V, VDDQ Rate of change
at 1V/ms
Tied to VDDQ through a 10kΩ
ENABLE, S_IN, VDDQOK
ENABLE, S_IN, VDDQOK
V_T-LOW Threshold voltage for Logic Low
V_T-HIGH
I_ITERN
ΔI_OUT
Threshold voltage for Logic High
(internally pulled high; can be left
floating to achieve logic high)
The ternary pin has 100kΩ to
AGND and another 100kΩ to an
internal 2.5V supply. If connecting
to AVIN recommend using a series
resistor. See Figure 7.
With 2 converters in parallel, the
difference between any two parts.
AVIN<50mV, R_TRACE< 2 mΩ
MIN
-25
1.8
2.0
2.0
TYP
AVIN
4
MAX UNITS
V
mA
+25
mV
50
μA
0.4
V
V
0.4
V
V
0.4
V
2.7
V
See
Figure
μA
7.
+/-10
%
Note 1: Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
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