EN2340QI Datasheet, PDF (3/20 Pages) Enpirion, Inc. – 204A Voltage Mode Synchronous Buck PWM

PIN
29-34
35-41
42
43
44
45
46
47
48
49
50
51
52, 53,
60
54
55
56
57
58
69
EN2340QI
NAME I/O
FUNCTION
PGND
G
Input/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
PVIN
P
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 29-34.
Internal 3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications where
AVINO O operation from a single input voltage (PVIN) is required. If AVINO is being used, place a
1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to AVINO.
PG I/O Place a 0.1µF, X5R/X7R, capacitor between this pin and BTMP.
BTMP I/O See pin 43 description.
VDDB
O
Internal regulated voltage used for the internal control circuitry. Place a 1.0µF, X7R,
capacitor between this pin and BGND.
BGND G See pin 45 description.
S_IN
I
Digital Input. This pin accepts either an input clock to phase lock the internal switching
frequency or a S_OUT signal from another EN2340QI. Leave this pin floating if not used.
S_OUT O Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.
POK
O
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.
ENABLE
I
Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start.
Applying a logic Low disables the output. Do not leave floating.
AVIN
P
3.3V Input power supply for the controller. Place a 0.1µF, X7R, capacitor between AVIN
and AGND.
AGND
G
Analog Ground. This is the Ground return for the controller. Needs to be connected to a
quiet ground.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VFB I/O VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
EAOUT O Optional Error Amplifier output. Allows for customization of the control loop.
SS
I/O
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
Programmable over-current protection. Placement of a resistor on this pin will adjust the
RCLX I/O over-current protection threshold. See Table 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electrical Characteristics table.
FADJ
Adding a resistor (R_FS) to this pin will adjust the switching frequency of the EN2340QI. See
I/O Table 1 for suggested resistor values on R_FS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave floating.
PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes.
©Enpirion 2012 all rights reserved, E&OE
06878
Enpirion Confidential
April 16, 2012
www.enpirion.com, Page 3
Rev: B