V6118 Datasheet, PDF (4/15 Pages) EM Microelectronic - MARIN SA – 2, 4 and 8 Multiplex LCD Driver

R
Timing Waveforms
V6118
V6118 Data Transfer Cycle, COL Inactive
Address Bits
Display RAM
Addr. 1 to Addr. n*
V6118 2 V6118 4 V6118 8
Address
LCD Row
(Note1)
10
1000
10000000 10000000
Row 1
01
0100
01000000 01000000
Row 2
0010
00100000 00100000
Row 3
0001
00010000 00010000
Row 4
00001000 00001000
Row 5
00000100 00000100
Row 6
00000010 00000010
Row 7
00000001 00000001
Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
Fig. 3
V6118 as a row and column driver ( COL inactive)
40 bit load cycle, RAM address provided by
address command bits 1 to (n*).
V6118 Data Transfer Cycle, COL Active
Address Bits
Display RAM
Addr. 1 to Addr. 8
V6118 2
V6118 4
V6118 8
Address
LCD Row
(Note1)
10000000 100000000 10000000 10000000 Row 1
01000000 01000000 01000000 01000000 Row 2
00100000 00100000 00100000 Row 3
00010000 00010000 00010000 Row 4
00001000 00001000 Row 5
00000100 00000100 Row 6
00000010 00000010 Row 7
00000001 00000001 Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
Fig. 4
V6118 as a column driver ( COL active)
48 bit load cycle, RAM address provided by
address command bits 1 to 8.
Fig. 5
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