EM6821 Datasheet, PDF (33/68 Pages) EM Microelectronic - MARIN SA – Ultra Low Power uController with 4x20 LCD Driver

R
EM6821
8.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[0]
or PA[3] input are counted. In this mode the counting will start directly on the next active clock edge on the
selected port A input.
The Event Count mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’.PA[3] and PA[0]
inputs can be inverted depending on register OPTIntEdgPA and should be debounced. The debouncer is
switched on in register OPTDebIntPA bits NoDebIntPA[3,0]=0. Its frequency depends on the bit DebSel from
register RegPresc setting. The inversion of the internal clock signal derived from PA[3] or PA[0] is active with
IntEdgPA[3] respectively IntEdgPA[0] equal to 1. Refer also to Figure 10 for internal clock signal
generation.
Figure 24. Internal Clock Synchronization
Ck
Ck
Start
Start
Count[9:0]
+/-1
EvCount = 0
Count[9:0]
+/-1
EvCount = 0
Ck
Start
Count[9:0]
EvCount = 1
Ck
Start
Count[9:0]
+/-1
EvCount = 1
8.4 Compare Function
A previously loaded register value (CReg[9:0]) can be compared against the actual counter value
(Count[9:0]). If the two are matching (equality) then an interrupt (IRQComp) is generated. The compare
function is switched on with the bit EnComp in the register RegCCntl2. With EnComp = 0 no IRQComp is
generated. Starting the counter with the same value as the compare register is possible, no IRQ is generated
on start. Full or Limited bit compare are possible, defined by bit SelIntFull in register RegSysCntl1.
EnComp must be written after a load operation (Load = 1). Every load operation resets the bit EnComp.
Full bit compare function.
Bit SelIntFull is set to ‘1’. The function behaves as described above independent of the selected counter
length. Limited bit counting together with full bit compare can be used to generate a certain amount of
IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter would
have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.
EnComp must be cleared before setting SelIntFull and before starting the counter again. Be careful, PWMOn
also redefines the port B PB[3] output data.(refer to section 8.5).
Limited bit compare
With the bit SelIntFull set to ‘0’ (default) the compare function will only take as many bits into account as
defined by the counter length selection BitSel[1:0] (see chapter 8.1).
8.5 Pulse Width Modulation (PWM)
The PWM generator uses the behavior of the Compare function (see above) so EnComp must be set to
activate the PWM function.. At each Roll Over or Compare Match the PWM state - which is output on port B
PB[3] - will toggle. The start value on PB[3] is forced while EnComp is 0 the value is depending on the up or
down count mode. Every counter value load operation resets the bit EnComp and therefore the PWM start
value is reinstalled.
Setting PWMOn to ‘1’ in register RegPresc routes the counter PWM output to port B terminal PB[3]. Insure that
PB[3] is set to output mode . Refer to section 6.4 for the port B setup.
The PWM signal generation is independent of the limited or full bit compare selection bit SelIntFull. However if
SelIntFull = 1 (FULL) and the counter compare function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined by the value of the
unused counter bits. It will count from the start value until the IRQComp match.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down count mode.
Copyright © 2005, EM Microelectronic-Marin SA
33
www.emmicroelectronic.com