EM6682 Datasheet, PDF (24/61 Pages) EM Microelectronic - MARIN SA – Ultra Low Power 8-pin Microcontroller

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EM6682
Figure 17. Example of Basic Serial Port Connections
EM6682
PA[1] ; SCLKOut
PA[2] ; SOUT
PA[0] ; SIN
Ready
PA[3] ; Status
Master Mode
External
Serial Clock In
Serial Data In
Serial Data Out
Status Output
CS
EM6682
PA[1] ; SCLKIn
PA[2] ; SOUT
PA[0] ; SIN
PA[3] ; Status
Slave Mode
External
Serial Clock In
Serial Data In
Serial Data Out
Ready
optional connection
7.3 Serial Interface Registers
Table 7.3.1 Register RegSCntl1
Bit
Name
Reset R/W
Description
3
MS1
0
R/W
Frequency selection
2
MS0
0
R/W
Frequency selection
1
POSnNeg
0
R/W
Positive or negative clock edge selection for shift operation
0
MSBnLSB
0
R/W
Shift MSB or LSB value first (0=LSB first)
Default "0" is: Slave mode external clock, negative edge, LSB first
Table 7.3.2 Frequency and Master Slave Mode Selection
MS1
MS0
0
0
0
1
1
0
1
1
Description
Slave mode: Clock from external
Master mode: ck[14], System clock / 4
Master mode: ck[15], System clock / 2
Master mode: ck[16], System clock
Table 7.3.3 Register RegSCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Enabling the interface,
2
Status
0
R/W
Ready or Chip Select output on PA[3]
1
RCoscOff
0
R/W
RC oscillator off when set to ‘1’ and if ExtCPUclkON is ‘1’
0
OM[0]
0
R/W Direct shift output when ‘0’ ; Output re-synchronised when ‘1’
Default "0" is: Interface disabled, status 0, direct shift output.
Table 7.3.4 Register RegSDataL
Bit
Name
Reset
R/W
3
SerDataL[3]
0
R/W
2
SerDataL[2]
0
R/W
1
SerDataL[1]
0
R/W
0
SerDataL[0]
0
R/W
Default "0" is: Data equal 0.
Description
Serial data low nibble
Serial data low nibble
Serial data low nibble
Serial data low nibble
Table 7.3.5 Register RegSDataH
Bit
Name
Reset
R/W
3
SerDataH[3]
2
SerDataH[2]
1
SerDataH[1]
0
SerDataH[0]
0
R/W
0
R/W
0
R/W
0
R/W
Default "0" is: Data equal 0.
Description
Serial data high nibble
Serial data high nibble
Serial data high nibble
Serial data high nibble
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