EM6125 Datasheet, PDF (14/43 Pages) EM Microelectronic - MARIN SA – Digitally programmable 65 and 81 multiplex rate LCD Controller and Driver

EM6125
8.4.2 Read Mode (RW = 1)
EM6125 will output one status byte after slave address. This status byte consists in 8 initialization bits previously set by
command bytes or the reset cycle (see Table 4: EM6125 instructions).
First byte send:
0 0 0 0 0 0 0 RW
Control Byte:
MSB
LSB
C0 DC Test[2]Test[1]Test[0] Ini[2] Ini[1] Ini[0] A
Data Byte:
MSB
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A
EM6125
Slave Address
Write mode:
Acknowledge
from EM6125
Acknowledge
from EM6125
A ck n o w le d g e
from EM6125
A ck n o w le d g e
from EM6125
Acknowledge
from EM6125
S 0 0 0 0 0 0 0 0A 1
Control Byte
A
Data Byte
Slave
Address
2n ^≥ 0 bytes
C0
A0
Control Byte
1 byte
C0
A
Data Byte
n ^≥ 0 bytes
AP
W rite
Mode
Read mode:
Acknowledge
from EM6125
Acknowledge
from master
S0 0 0 0 0 0 0 1A1
Status Byte
AP
Slave
Address
Figure 12: I²C protocol description
8.5 Display Data RAM
The EM6125 contains a RAM, which stores the display data; there is a one to one correspondence between the bit stored in
the RAM and one LCD pixel.
8.5.1 DDRAM description
DDRAM consists in:
1 bank of 118 bits (row 0)
8 banks of 118 bytes (rows 1 to 64)
2 banks of 102 bytes (rows 65 to 80)
DDRAM is read row by row for display refresh. Each row corresponds to one pad, which is activated when the
corresponding row is read.
DDRAM is accessed via the interface. Bytes are stored at the column specified by x-address pointer and the bank specified
by y-address pointer. These pointers are set by the corresponding instruction “Initialization 1” and “Initialization 2” and are
automatically incremented or decrement after each byte written in the DDRAM (see
DDRAM addressing and Table 5: Internal functions after reset.)
For bank 0 only data byte 7 (DB7) is stored in row 0, DB6 to DB0 are not used. For bank 1 to 10 (y-address = 1 to 10), DBX
is stored at row ((8 x y-address)-X).
Copyright  2001, EM Microelectronic-Marin SA
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