V3022 Datasheet, PDF (1/15 Pages) EM Microelectronic - MARIN SA – Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming and High Level Integration

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EM MICROELECTRONIC - MARIN SA
V3022
Very Low Power 8-Bit 32 kHz RTC Module with Digital
Trimming and High Level Integration
Description
The V3022 is a low power CMOS real time clock with a
built in crystal. Standby current is typically 1.2 µA and the
access time is 50 ns. The interface is 8 bits with
multiplexed address and data bus. Multiplexing of
address and data is handled by the input line A /D. There
are no busy flags in the V3022, internal time update
cycles are invisible to the user's software. Time data can
be read from the V3022 in 12 or 24 hour data formats. An
external signal puts the V3022 in standby mode. Even in
standby, the V3022 pulls the IRQ pin active low on an
internal alarm interrupt. Calendar functions include leap
year correction and week number calculation. Time
precision can be achieved by digital trimming.
Applications
Industrial controllers
Alarm systems with periodic wake up
PABX and telephone systems
Point of sale terminals
Automotive electronics
Features
Built-in crystal with digital trimming and temperature
compensation facilities
50 ns access time with 50 pF load capacitance
Standby on power down typically 1.2 µA
Wide voltage range, 2.0V to 5.5V
Universal interface compatible with both Intel and
Motorola
Simple 8 bit interface with no delays or busy flags
Power fail input disables during power up / down of
reset
Bus can be in tri-state in power fail mode
12 or 24 hour data formats
Time to 1/100 of a second
Leap year correction and week number calculation
Alarm and timer interrupts
Programmable interrupts: 10 ms, 100 ms, s or min
Sleep mode capability
Alarm programmable up to one month
Timer measures elapsed time up to 24 hours
Temperature range: -40°C to +85°C
Package SO28
Typical Operating Configuration
CPU
Address
Decoder
CS
IRQ
RD
WR ^V3022
A/D
AD0 to AD7
CS
RD
WR
Copyright © 2004, EM Microelectronic-Marin SA
Fig. 1
Pin Assignment
SO28
TEST
PF
AD0
AD1
NC
AD2
AD3
A/D
IRQ
V_SS
V_SS
V_SS
V_SS
V_SS
1
V3022
NC
AD7
AD6
AD5
NC
AD4
RD
WR
CS
V_DD
V_DD
V_DD
V_DD
V_DD
Fig. 2
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