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EMTG56 Datasheet, PDF (1/3 Pages) EM Microelectronic - MARIN SA – 56KB Ultra Low Cost Flash Smart Card IC | |||
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EM MICROELECTRONIC - MARIN SA
TheseusTM Gold 56
EMTG56
56KB Ultra Low Cost Flash Smart Card IC
Environment
 Voltage Supply Class A, B: 3.0V to 5.0V ± 10%
 -25 to +85 °C Operating Temperature
 Max supply current 6mA @ 15MHz, Class B
 > 4 kV ESD Protection HBM
CPU
 Software compatible CMOS 80X51 industry standard
 Accelerated architecture with 16 bit CPU performance level
 Up to 30 MHz internal CPU clock
Idle Modes
 Idle and Stop mode selectable modes
 NVM update operation with CPU in idle mode
 IO Transmission and Reception with CPU in idle mode
 Max Idle current / Clock stopped: 100 uA
Security
 Hardware Random Number Generator FIPS140-2
 Unique chip identification number
 Notification of tampering
 IC operates under regulated voltage and internal clock
 DPA/SPA resistance mechanisms
 Under / Over voltage sensors (Vcc)
Memory Control
 General Purpose Non Volatile Memory: GPNVM
 Secure Memory Management Mechanism
 Fast Byte program: 40 us / Byte
 GPNVM Page Erase: 2 ms
I/O
 ISO 7816-3 compliant electrical interface
 ISO 7816-3 compliant interface with T=0 and T=1 protocols
 ETU Timer/Counter replacing 8051 T0/T1 Timers
Memories
 1024 bytes RAM (256B Local RAM + 768B XRAM)
 56KB GPNVM (User) = 448 pages of 128 bytes
 User Code, constant storage (ROM)
 User Non Volatile Data storage (EEPROM)
 1KB GPNVM (System) = 8 pages of 128 bytes
 System parameters
 Loader extensions
 Backup buffer / hard API code
 10 year data retention for EEPROM / OTPROM
 GPNVM Cycling Endurance > 100 K cycles
 BootROM loader T0 and T14 compatible
 Boot loader commands set extension capabilities
Chip Forms
 8â Wafer sawn or unsawn
 Back grinding and distressing options
 180 microns max thickness
 Modules
Typical Application:
 SIM card GSM Phase2+ 32KB
9 Development tools fully integrated within Keil uVision2/3
9 DevKit emulator, examples, documentation samples
EMTG56
SECURITY MODULE
UVD / OVD
DPA / SPA
protections
Random Number
Generator
Power Management System
30MHz on-chip Oscillator
Controlled Clock Divider
Internal VDD
Power-on Reset
A, B on-chip
Voltage Regulator
Fast Architecture
80X51 Core
256 Bytes RAM
ETU Timer
ISO 7816-3
Interface 3G
Secure Memory Management
Boot ROM
GPNVM
768 Bytes 56K Bytes [ code]
[ data ]
Loader System (1KB)
RAM
GPNVM User
Flexible code / data memory allocation
Copyright © 2005, EM Microelectronic-Marin SA
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