EM680FU16 Datasheet, PDF (5/11 Pages) Emerging Memory & Logic Solutions Inc – 512K x16 bit Low Power and Low Voltage Full CMOS Static RAM

merging Memory & Logic Solutions Inc.
EM680FU16 Series
Low Power, 512Kx16 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
CL¹⁾ = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R₁=3070 ohm, R₂=3150 ohm
3. V_TM=2.8V
CL¹⁾
V_TM3)
R₁₂₎
R₂₂₎
READ CYCLE (V_cc =2.7 to 3.3V, Gnd = 0V, T_A = -40^oC to +85^oC)
Parameter
Symbol
55ns
Min
Max
70ns
Min
Max
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB acess time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to how-Z output
Output disable to high-Z output
Output hold from address change
t_RC
t_AA
t_co1, t_co2
t_{O E}
t_BA
t_LZ1, t_LZ2
t_BLZ
t_OLZ
t_HZ1, t_HZ2
t_BHZ
t_OHZ
t_OH
55
-
70
-
-
55
-
70
-
55
-
70
-
30
-
35
55
70
5
-
5
-
10
-
5
-
10
-
5
-
0
20
0
25
0
20
0
25
0
20
0
25
10
-
10
-
WRITE CYCLE (V_cc =2.7 to 3.3V, Gnd = 0V, T_A = -40^oC to +85^oC)
Parameter
Symbol
55ns
Min
Max
70ns
Min
Max
Write cycle time
t_WC
55
-
70
-
Chip select to end of write
t_CW1, t_CW2
45
-
60
-
Address setup time
t_As
0
-
0
-
Address valid to end of write
t_AW
45
-
60
-
UB, LB valid to end of write
t_BW
45
-
60
-
Write pulse width
t_{W P}
45
-
55
-
Write recovery time
t_WR
0
-
0
-
Write to ouput high-Z
t_WHZ
0
20
0
25
Data to write time overlap
t_DW
30
30
Data hold from write time
t_DH
0
-
0
-
End write to output low-Z
t_{O W}
5
-
5
-
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns