EM640FU8E Datasheet, PDF (4/11 Pages) Emerging Memory & Logic Solutions Inc – 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

merging Memory & Logic Solutions Inc.
EM640FU8E Series
Low Power, 512Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS ¹⁾
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
V_CC
V_SS
V_IH
V_IL
Min
2.7
0
2.2
-0.2 ^{3 )}
1. TA= -40 to 85^oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Typ
Max
Unit
3.0
3.3
V
0
0
V
-
V_CC + 0.2²⁾
V
-
0.6
V
CAPACITANCE¹⁾ (f =1MHz, T_A=25^oC)
Item
Input capacitance
Input/Ouput capacitance
Symbol
C_IN
C_IO
1. Capacitance is sampled, not 100% tested
Test Condition
Min
Max
Unit
V_IN=0V
-
8
pF
V_IO =0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Operating power supply
Average operating current
Output low voltage
Output high voltage
Standby Current (TTL)
Standby Current (CMOS)
Symbol
Test Conditions
I_LI
V _IN=V _SS to V_CC
I_LO
CS₁= V_IH , CS₂=V_IL or OE=V _IH or WE=V_IL, V_IO= V_SS to V_CC
I_CC
I _IO=0mA, CS ₁=V _IL, CS ₂=WE = V_IH , V_{I N}=V_{I H} or V_IL
I_CC1
I_CC2
Cycle time=1µs, 100% duty, I _IO=0mA,
CS₁< 0.2V, CS₂>V_CC -0.2V,
V _IN< 0.2V or V_IN >V_CC-0.2V
Cycle time = Min, I_IO=0mA, 100% duty,
CS₁=V _IL, CS₂=V _IH, V_IN=V _IL or V_{I H}
55ns
70ns
V_OL
V_{O H}
I_OL = 2.1mA
I _OH = -1.0mA
I_SB
CS₁= V_IH , CS₂=V_IL, Other inputs=V _IH or V _IL
CS₁>V_CC-0.2V, CS ₂>V _{C C}-0.2V (CS ₁ controlled)
or 0V<CS₂<0.2V (CS₂ controlled),
I_SB1
Other inputs=0~V_CC
(Typ. condition : V _{C C}=3.0V @ 25^oC)
LL
LF
(Max. condition : V_CC=3.3V @ 85^oC)
Min Typ Max
-1
-
1
-1
-
1
-
-
2
-
-
2
-
-
20
-
-
15
-
- 0.4
2.2
-
-
-
- 0.3
-
1
5
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
4