RMLD232UAW Datasheet, PDF (31/50 Pages) Emerging Memory & Logic Solutions Inc – 2M x 32 bit Low Power DDR SDRAM

Advanced
64Mb Low Power DDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V_SS = 0V, Temp = -25 to 85 ¦ )
Parameter
Symbol
Test Condition
DDR
266
DDR
222
Unit
Operating Current
t_RC=t_RCmin; t_CK=t_CKmin ; CKE is HIGH; CS is HIGH between valid
(One Bank Active/Precharge
I_DD0
commands; address inputs are switching every two clock cycles;
80
current)
Data bus inputs are stable
75
§
Operating Current
(One Bank Active-Read-Pre-
charge current; Burst=4)
I_DD1
t_RC=t_RCmin;
t_CK=t_CKmin
;
CKE
is
HIGH;
I_OUT
=
0

;
Address and control inputs changing once per clock cycle
100
95
§
All banks idle, CKE is LOW; CS is HIGH, t_CK=t_CKmin;
I_DD2P _{Address and control inputs are switching every two clock cycles;}
0.5
Precharge Standby
Data bus inputs are stable
Current in power-down
§
mode
All banks idle, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH;
I_DD2PS address and control inputs are switching every two clock cycles;
0.5
Data bus inputs are stable
All banks idle, CKE is HIGH; CS is HIGH, t_CK=t_CKmin; Address and
I_DD2N _{control inputs are switching every two clock cycles;}
20
Precharge Standby
Data bus inputs are stable
Current in non power-down
mode
All banks idle, CKE is HIGH; CS is HIGH, CK=LOW, CK=HIGH;
I_DD2NS Address and control inputs are switching every two clock cycles;
10
Data bus inputs are stable
15
§
10
One bank active, CKE is LOW; CS is HIGH, t_CK=t_CKmin;
I_DD3P _{Address and control inputs switching every two clock cycles;}
5
Active Standby Current
Data bus inputs are stable
in power-down mode
§
One bank active, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH;
I_DD3PS Address and control inputs are switching every two clock cycles;
3
Data bus inputs are stable
Active Standby Current
in non power-down mode
(One Bank Active)
One bank active, CKE is HIGH; CS is HIGH, t_CK=t_CKmin;
I_DD3N _{Address and control inputs switching every two clock cycles;}
25
Data bus inputs are stable
One bank active, CKE is HiGH; CS is HIGH, CK=LOW, CK=HIGH;
I_DD3NS Address and control inputs are switching every two clock cycles;
20
Data bus inputs are stable
20
§
15
§
Operating Current
(Burst Mode)
One bank active; BL=4; CL=3; t_CK=t_CKmin; Continuous read bursts;
I_DD4R
I_OUT
=
0

; Address inputs are switching;
120
50% data change each burst tranfer
I_DD4W
One bank active; BL=4; t_CK=t_CKmin; Continuous write bursts;
Address inputs are switching; 50% Data change each burst transfer
100
115
§
95
§
Refresh Current
I_DD5
t_RC=t_RFCmin; t_CK=t_CKmin; burst refresh; CKE is HIGH;
Address and control inputs are switching; Data businputs are stable
100
95
§
Self Refresh Current
I_DD6
CKE is LOW; t_CK= t_CKmin ;
Extended Mode Register set to all 0’s; address
and control inputs are stable; Data bus inputs
are stable
TCSR Range
4 Banks
2 Banks
Max
Max
45
85
¦
220
250
170
190
¨
1 Bank
135
150
Deep Power Down Current
I_DD8*1 Address and control inputs are stable; Data bus inputs are stable
10
¨
NOTE :
1. DPD (Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Ramsway for more information.
2. I_DD specifications are tested after the device is properly intialized.
3. Input slew rate is 1V/ .
©
4. Definitions for I_DD:
LOW is defined as V_IN  0.1*V_DDQ;
HIGH is defined as V_IN  0.9*V_DDQ;
31
Rev 0.7