EMD56164P Datasheet, PDF (24/45 Pages) Emerging Memory & Logic Solutions Inc – 256M: 16M x 16 Mobile DDR SDRAM

Preliminary
EMD56164P
256M: 16M x 16 Mobile DDR SDRAM
Read Interrupted by a Read < Burst Length=4, CAS Latency = 2 >
0
1
2
3
4
5
6
CKB
CK
Command READ A
READ B
NOP
NOP
NOP
NOP
NOP
7
NOP
8
NOP
DQS
CL2
DQ’s
Dout a0 Dout a1 Dout b0 Dout b1 Dout b2 Dout b3
Truncated READs
Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency
is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ
command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architec-
ture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If
truncation is necessary, the BURST TERMINATE command must be used.
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto
precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command,
where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Follow-
ing the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note: Part of the row precharge time is hidden during the access of the last data elements.
Read Interrupted by a Write & Burst Stop < Burst Length=4, CAS Latency = 2 >
0
1
2
3
4
5
6
7
CKB
CK
Command READ
Burst Stop
NOP
WRITE
NOP
NOP
NOP
NOP
8
NOP
DQS
CL2
DQ’s
Dout 0 Dout 1
Din 0 Din 1 Din 2 Din 3
Read Interrupted by a Precharge < Burst Length=8, CAS Latency = 2 >
0
1
CKB
CK
1tCK
Command READ
Precharge
2
NOP
3
NOP
4
NOP
5
6
NOP
NOP
DQS
CL2
DQ’s
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
7
NOP
8
NOP
24
Rev 0.0