RMS132UAW Datasheet, PDF (21/26 Pages) Emerging Memory & Logic Solutions Inc – 512K x 32Bits x 2Banks Low Power Synchronous DRAM

RMS132UAW
Advance Information
Table12: DC Characteristic (DC operating conditions unless otherwise noted)
Parameter
Operating Current
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Burst Mode Operating Current
Auto Refresh Current (4K Cycle)
PASR
TCSR
Self
Refresh
Current
2 Banks
1 Bank
45~85°C
-25~45°C
45~85°C
-25~45°C
Deep Power Down Mode Current
Sym
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
Test Condition
Speed
Unit Note
-60 -75 -10
Burst Length=1, One Bank Active,
tRC ≥ tRC(min) IOL = 0 mA
45
mA
1
CKE ≤ VIL(max), tCK = 10ns
CKE & CLK ≤ VIL(max), tCK = ∞
80
uA
80
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
6
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
1
CKE ≤ VIL(max), tCK = 10ns
CKE & CLK ≤ VIL(max), tCK = ∞
0.5
mA
0.5
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
15
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
6
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
80 75 70 mA
1
tRC ≥ tRFC(min), All Banks Active
40
mA
2
ICC6 CKE ≤ 0.2V
ICC7
80~100
60~80
uA
70~90
50~70
10
uA
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com.
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