EMC326SP16AK Datasheet, PDF (15/52 Pages) Emerging Memory & Logic Solutions Inc – 2Mx16 bit CellularRAM AD-MUX

Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during the
entire sequence. The ADV# signal can be used to latch the target address. CE# can remain LOW when the device is transitioning
between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed t_CEM. Mixed-mode operation
facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 36 on page 49 for the “Asynchronous
WRITE Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal(See Figure 8). The shared
WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
Figure 8: Wired or WAIT Configuration
READY
Processor
CellularRAM
WAIT
WAIT
Other
Device
WAIT
Other
Device
External
Pull-Up
Pull-Down
Resistor
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires addi-
tional time before data can be transferred. For burst READ operations, WAIT will remain active until valid data is output from the device.
For burst WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When
WAIT transitions to an inactive state, the data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data
corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ operations
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed(See Figure 7 ). When the refresh operation has completed, the burst READ operation will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new
row to be accessed.
WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during asynchronous WRITE
operations. WAIT should be ignored during all asynchronous operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal.
However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of the row. If WAIT is
not monitored, the controller must properly terminate all burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written
is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When
both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data.
Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
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