EMD56324P Datasheet, PDF (14/45 Pages) Emerging Memory & Logic Solutions Inc – 256M: 8M x 32 Mobile DDR SDRAM

Preliminary
EMD56324P
256M: 8M x 32 Mobile DDR SDRAM
Extended Mode Register
The extended mode register controls functions specific to low power operation. These additional functions include
drive strength, temperature compensated self refresh, and partial array self refresh.
This device has default values for the extended mode register (if not programmed, the device will operate with the
default values . PASR = Full Array, DS = Full Drive).
Temperature Compensated Self Refresh
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self
refresh oscillator on the device. Programming of the temperature compensated self refresh (TCSR) bits will have no
effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the
device temperature.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of
memory that will be refreshed during SELF REFRESH. Low Power DDR SDRAM supports 3 kinds of PASR in self
refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.
Partial Self
Refresh Area
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- Full Array
BA1=1 BA1=1
BA0=0 BA0=1
- 1/2 Array
BA1=1 BA1=1
BA0=0 BA0=1
- 1/4 Array
Output Driver Strength
Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to
control the drive strength of the output buffers is available. Drive strength should be selected based on the expected
loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of
the DQ outputs.
Stopping the External Clock
One method of controlling the power efficiency in applications is to throttle the clock which controls the Mobile DDR
SDRAM. There are two basic ways to control the clock:
1. Change the clock frequency, when the data transfers require a different rate of speed.
2. Stopping the clock altogether.
Both of these are specific to the application and its requirements and both allow power savings due to possible less
transitions on the clock path.
The Mobile DDR SDRAM allows the clock to change frequency during operation, only if all the timing parameters are
met with respect to that change and all refresh requirements are satisfied.
The clock can also be stopped all together, if there are no data accesses in progress, either WRITEs or READs that
would be effected by this change; i.e., if a WRITE or a READ is in progress the entire data burst must be through the
pipeline prior to stopping the clock. CKE must be held HIGH with CK = LOW and CKB = HIGH for the full duration of
the clock stop mode. One clock cycle and at least one NOP is required after the clock is restarted before a valid com-
mand can be issued.
It is recommended that the Mobile DDR SDRAM should be in a precharged state if any changes to the clock frequency
are expected. This will eliminate timing violations that may otherwise occur during normal operational accesses.
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