EMD12164P Datasheet, PDF (13/45 Pages) Emerging Memory & Logic Solutions Inc – 512M: 32M x 16 Mobile DDR SDRAM

Preliminary
EMD12164P
512M: 32M x 16 Mobile DDR SDRAM
Register Definition
Mode Registers
The mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM. There are two mode
registers used to specify the operational characteristics of the device. The standard mode register, which exists for all
SDRAM devices, and the extended mode register, which exists on all Mobile SDRAM devices.
Standard Mode Register
The standard mode register definition includes the selection of a burst length, a burst type, a CAS latency and an oper-
ating mode, as shown in page 15. The standard mode register is programmed via the LOAD MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again. Reprogram-
ming the standard mode register will not alter the contents of the memory, provided it is performed correctly. The mode
register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or
interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
Note: Standard refers to meeting JEDEC-standard mode register definitions.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as
shown in page 15. The burst length determines the maximum number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4, or 8 are available for both the sequential and the interleaved
burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst
type and is selected by A3. The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address. See Table 17~19 on page 17 for more information.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first bit of output data. The latency can be set to 2 or 3 clocks, as shown in page 15.
For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at (n + 2
clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally be avail-
able at (n + 1 clock + tAC).
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER SET command with bits A7-A12 each
set to zero, and bits A0-A6 set to the desired values. All other combinations of values for A7-A12 are reserved for
future use and/or test modes. Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
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