EMP216MEAW Datasheet, PDF (11/14 Pages) Emerging Memory & Logic Solutions Inc – 2Mx16 Pseudo Static RAM

LOW POWER MODES
Mode Register Set
A20 ~ A5
A4
All 0
(Reserved for
future)
DPD
Enable/Disable
A3
Array Mode
Selection
Preliminary
EMP216MEAW Series
2Mx16 Pseudo Static RAM
A2
Array Half
Selection
A1
A0
Array Refresh Area Selection
DPD Enable / Disable
A4
Type
0
Deep Power Down Enable
1
DPD Disable (Default)
Array Mode Selection
A3
Type
0
Partial Array Refresh Mode (Default)
1
Reduced Memory Size Mode
Array Half Selection (Top/Down)
A2
Type
0
Bottom (Default)
1
Top
Array Refresh Area Selection
A1 A0
Type
00
Full Array (Default)
01
RFU (Reserved for future)
10
1/2 Array
11
1/4 Array
NOTES
1. The Partial Array Refresh and Deep Power Down mode is issued only during ZZ# low state.
2. The RMS (Reduced Memory Size) mode is enabled after ZZ# goes high and remains enabled after ZZ# goes high. To
change to a different mode, the mode register will have to be re-written.
3. If register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that
ZZ# is driven low and there is no MRS update. When ZZ# is driven high, all of the register settings will return to dafault state
for the part (i.e. full array refresh, Deep Power Down disabled.)
Mode Register Set UpdateTiming Diagram
t_WC
Address
CS#
LB#,UB#
t_CW
t_WR
t_AS
t_AW
t_BW
WE#
t_WP
ZZ#
t_ZZWE
NOTES
Register write start
Register write complete Register update complete
The register update takes place after over the ^tZZWE maximum time of 1us. Once the register is updated the next time ZZ#
goes low, without any updates to the register starting within the ^tZZWE maximum time of 1us, the part will refresh the array
selected. The data bus is a don’t care when ZZ# is low during the register updates.

Rev 0.0