EMP216MGAW Datasheet, PDF (10/12 Pages) Emerging Memory & Logic Solutions Inc – 2Mx16 Pseudo Static RAM

Preliminary
EMP216MGAW Series
2Mx16 Pseudo Static RAM
PAGE WRITE CYCLE (ZZ#=V_IH, 16 Words access)
t_MRC
Address
(A20~A4)
Address
(A3~A0)
t_WC
t_PC
t_PC
t_PC
t_PC
CS#
LB#,UB#
t_AS
WE#
Data In
High-Z
Data Out
t_WHZ
t_DW t_DH t_DW t_DH t_DW t_DH t_DW t_DH t_DW t_DH
Data Valid Data Valid Data Valid Data Valid Data Valid
t_OW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(t_WP) of low CS#, low WE# and low UB# or LB#. A write begins at the last
transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously
asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#.
The t_WP is measured from the beginning of write to the end of write.
2. t_CW is measured from CS# going low to end of write.
3. t_AS is measured from the address valid to the beginning of write.
4. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as CS# or WE# going high.
5. Do not Access device with cycle timing shorter than t_WC for continuous periods > 20us.
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