EM78452 Datasheet, PDF (42/54 Pages) ELAN Microelectronics Corp – 8-Bit Microcontroller

EM78452
8-Bit Microcontroller
Table 8 The Status of RST, T and P Being Affected by Events
Event
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-up on pin change during Sleep 2 mode
5.8 Interrupt
T
P
1
1
1
1
0
*P
1
0
P
P
*P: Previous value before reset
The EM78452 has the following interrupts.
1. /TCC overflow interrupt
2. External interrupt (/INT)
3. Serial Peripheral Interface (SPI) transmission completed interrupt.
4. Timer 1 overflow interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF
is the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, it will
cause the next instruction to be fetched from address 001H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in
the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI instruction. Note that reading R3F will obtain the output of
logic AND of R3F and IOCF (refer to Fig. 5-16). The RETI instruction exits the interrupt
routine and enables the global interrupt (execution of ENI instruction).
When an interrupt is generated by INT instruction (if enabled), it causes the next
instruction to be fetched from address 002H.
38 •
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)