EM78P330 Datasheet, PDF (34/112 Pages) ELAN Microelectronics Corp – 8-Bit Microprocessor with OTP ROM

EM78P330/331N
8-Bit Microprocessor with OTP ROM
Bit 1 (/PH81): Control bit used to enable the pull-low function of the P81 output pin.
Bit 0 (/PH80): Control bit used to enable the pull-low function of the P80 output pin.
6.1.44 Bank 3 RD (TMR1H: Most Significant Bits (Bit9 ~ Bit2) of
PWM1 Timer)
The contents of RD are read-only.
6.1.45 Bank 3 RE (TMR2H: Most Significant Bits (Bit 9 ~ Bit 2) of
PWM2 Timer)
The contents of RE are read-only.
6.1.46 Bank 3 RF (TMRL: Least Significant Bits of PWM Timer)
Bit 7
“0”
Bit 6
“0’
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR3[1] TMR3[0] TMR2[1] TMR2[0] TMR1[1] TMR1[0]
The contents of RF are read only,
Bit 7 ~ Bit 6: Unimplemented, read as “0”.
Bit 5 ~ Bit 4: (TMR3 [1], TMR3 [0]): Most Significant Bits of PWM3 Timer.
Bit 3 ~ Bit 2: (TMR2 [1], TMR2 [0]): Most Significant Bits of PWM2 Timer.
Bit 1 ~ Bit 0: (TMR1 [1], TMR1 [0]): Most Significant Bits of PWM1 Timer.
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator. The Accumulator is not an
addressable register.
6.2.2 CONT (Control Register)
Bit 7
INTE
Bit 6
INT
Bit 5
TS
Bit 4
TE
Bit 3
PSTE
Bit 2
PST2
Bit 1
PST1
Bit 0
PST0
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT pin
1 = interrupt occurs at the falling edge on the INT pin
Bit 6 (INT):
Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
TCC signal source
0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be 0.
1 = transition on the TCC pin
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Product Specification (V1.1) 03.13.2007
(This specification is subject to change without further notice)