EM78P870 Datasheet, PDF (31/48 Pages) ELAN Microelectronics Corp – 8 BIT MICROCONTROLLER

EM78P870
8-bit OTP Micro-controller
Set when counter1 timer overflows .
Bit 2 (CNT2) : Counter2 timer overflow interrupt flag
Set when counter2 timer overflows .
Bit 3 (INT0) : External INT0 pin interrupt flag
If PORT70 ,PORT71,PORT72 or PORT73 has a falling edge trigger signal. CPU will set this bit.
Bit 4 (INT1) : External INT1 pin interrupt flag
If PORT74 ,PORT75 or PORT76 has a falling edge trigger signal. CPU will set this bit.
Bit 5 (INT2) : External INT2 pin interrupt flag
If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal. CPU will set this
bit.
Bit 6 : unused
Bit 7 ( RBF) : Interrupt flag for SPI data complete
If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will
set this bit.
IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Signal
Trigger
<Note>
TCC
Time out
COUNTER1 Time out
COUNTER2 Time out
INT0
Falling edge
INT1
Falling edge
INT2
Falling/Falling&rising edge Controlled by CONT register
RBF
Rising edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers.
VII.4 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
5
4
3
2
INT_EDGE INT
TS
-
PAB PSR2
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2 PSR1 PSR0 TCC rate WDT rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
1
PSR1
0
PSR0
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* This specification is subject to be changed without notice.
28
8/19/2004 (V1.5)