EM78P915 Datasheet, PDF (28/60 Pages) ELAN Microelectronics Corp – 8-BIT MICRO-CONTROLLER

EM78P915
8-bit Micro-controller
Software design flow:
Step1: Port70 ~ port73 set to input mode
Step2: Port70~port73 pull high
Step3: Enable key scan signal
Step4: Once push a key. Set RA bit6 = “1” and switch to normal mode
Step5: Blank LCD. Disable scan key signal
Step6: Set portX as normal i/o. PortX sent probe signal to port70~73 and read port70~73. Get the key.
Note: a probe signal should be delay a instruction at least to another probe signal
Step7: Set portX to SEG port, enable LCD.
Note: one port must be port70~73 (INT0), and another port is the shared port like port9, port8, portC and portB.
PAGE 1 (Data RAM address8 ~ address11)
7
6
5
4
3
2
1
0
X
X
X
X
RAMA11 RAMA10 RAMA9 RAMA8
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0~Bit 4(RAMA8~RAMA11) : Data RAM address (address8 to address11) for RAM reading.
Bit 6 (Unused)
Bit 7 (Unused)
RF (Interrupt flags)
7
6
5
4
3
2
1
0
RBF/SDT FSK/CW INT2
SDTI
INT0
CNT2
CNT1
TCIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF): TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1(CNT1): Counter1 timer overflow interrupt flag
Set when counter1 timer overflows.
Bit 2(CNT2): Counter2 timer overflow interrupt flag
Set when counter2 timer overflows.
Bit 3(INT0): External INT0 pin interrupt flag
If PORT70, PORT7, PORT72 or PORT73 has a falling edge trigger signal. CPU will set this bit.
Bit 4(SDTI): SDT interrupt flag
Set when receive a SDT valid data.
Bit 5(INT2): External INT2 pin interrupt flag
If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal. CPU will set this bit.
Bit 6(FSK/CW): FSK data or Call waiting data interrupt flag.
If FSKDATA or CAS has a falling edge trigger signal, CPU will set this bit.
Bit 7(RBF/STD): SPI data transfer complete or DTMF receiver signal valid interrupt
If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit.
Or DTMF receiver's STD signal has a rising edge signal (DTMF decode a DTMF signal).
IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
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* This specification is subject to be changed without notice.
2005/12/21 (V2.0)