EM78P157N Datasheet, PDF (28/56 Pages) ELAN Microelectronics Corp – 8-Bit Microcontroller with OTP ROM

EM78P157N
8-Bit Microcontroller with OTP ROM
4.6 Interrupt
The EM78P157N has three falling-edge interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g.,
"MOV R6,R6") is necessary. Each Port 6 pin of will have this feature when its status
changes. Any pin configured as output or P60 pin configured as “/INT,” is excluded
from this function. The Port 6 Input Status Change Interrupt can wake up the
EM78P157N from the sleep mode if Port 6 is enabled prior to going into the sleep mode
by executing SLEP instruction. When the chip wakes-up, the controller will continue to
execute the succeeding address if the global interrupt is disabled or branches to the
interrupt vector 008H if the global interrupt is enabled.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the enabled
interrupts occurs, the next instruction will be fetched from address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or ENI execution. Note that the outcome of RF will be the logic
AND of RF and IOCF (refer to Fig. 4-7 above). The RETI instruction ends the interrupt
routine and enables the global interrupt (execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from address 001H.
VCC
/IRQn
D
P
R
Q
CLK
_
CQ
L
RF
RFRD
IRQn
IRQm
INT
ENI/DISI
/RESET
Q
P
R
D
IOD
_
IOCF ^Q
CLK
C
L
IOCFWR
IOCFRD
RFWR
Fig. 4-8 Interrupt Input Circuit
22 •
Product Specification (V1.0) 09.22.2005
(This specification is subject to change without further notice)