EM78M680 Datasheet, PDF (19/53 Pages) ELAN Microelectronics Corp – USB Full Speed Microcontroller

Contents
1
0
Bank 2
1
1
Bank 3
6.2.1.6 R5 (Port 5 I/O Register) Default Value: (0B_0000_0000)
Bit 7
P57
Bit 6
P56
Bit 5
P55
Bit 4
P54
Bit 3
P53
Bit 2
P52
Bit 1
P51
Bit 0
P50
6.2.1.7 R6 (Port 6 I/O Register) Default Value: (0B_0000_0000)
Bit 7
P67
Bit 6
P66
Bit 5
P65
Bit 4
P64
Bit 3
P63
Bit 2
P62
Bit 1
P61
Bit 0
P60
6.2.1.8 R7 (Port 7 I/O Register) Default Value: (0B_0000_0000)
Bit 7
P77
Bit 6
P76
Bit 5
D-
Bit 4
D+
Bit 3
−
Bit 2
P72
Bit 1
P71
Bit 0
P70
6.2.1.9 R8 (Port 8 I/O Register) Default Value: (0B_0000_0000)
Bit 7
P87
Bit 6
P86
Bit 5
P85
Bit 4
P84
Bit 3
P83
Bit 2
P82
Bit 1
P81
Bit 0
P80
6.2.1.10 R9 (Port 9 I/O Register) Default Value: (0B_0000_0000)
Bit 7
−
Bit 6
P96
Bit 5
P95
Bit 4
P94
Bit 3
P93
Bit 2
P92
Bit 1
P91
Bit 0
P90
6.2.1.11 RA (USB Endpoint 0 Status Register): Default Value: (0B0000_0000)
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
Extr _R Remote Status EP0_W EP0_R Dev _Resume UDC_Suspend UDC_Writing STALL
RA [0]
STALL flag. When the MCU receives an unsupported command or
invalid parameters from host, this bit will be set to 1 by the firmware to
notify the UDC to return a STALL handshake. When a successful setup
transaction is received, this bit is cleared automatically. This bit is both
readable and writable.
RA [1]
UDC Writing flag. Read only. When this bit is equal to “1,” it indicates
that the UDC is writing da0ta into the EP0’s FIFO or reading data from it.
During this time, the firmware will avoid accessing the FIFO until the
UDC finishes writing or reading. This bit is only readable.
1 : EP0’s FIFO is busy
0 : EP0’s FIFO is free for data transition. ACK, NAK are reset.
RA [2]
UDC Suspend flag. If this bit is equal to 1, it indicates that the USB bus
has no traffic for a specified period of 3.0 ms. This bit will also be
cleared automatically when a bus activity takes place. This bit is only
readable.
Product Specification (V1.11) 02.10.2007
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