EPL09060 Datasheet, PDF (15/54 Pages) ELAN Microelectronics Corp – 9 COM/ 60 SEG v

7.2.1 Display Data RAM (DDRAM)
EPL09060
9 COM/60 SEG LCD Driver
D is p la y D a ta R A M
C o lu m n A d d re s s D e c o d e r
C o lu m n A d d re s s C o u n te r
C o lu m n A d d re s s R e g is te r
Figure 6 Display Data RAM Diagram
The display data RAM (DDRAM) stores pixel data for the LCD. It is a 43-row × 102-
column addressable array. It is possible to access any required bit by specifying the
page address and the column address. The 43 rows are divided into five pages of
eight lines, one page with two lines (D0, D1) and the seventh page with a single line
(D0 only).
Each bit in the Display Data RAM corresponds to each pixel of the LCD panel. Each
bit in the Display Data RAM corresponds to each pixel of the LCD panel and controls
the display by applying the following bit data.
When in Normal Display : On="1" , Off="0"
When in Inverse Display : On="0" , Off="1"
(Refer to “Inverse Display On/Off” instruction for more details.)
0000000
0111110
0100000
0111110
0100000
0111110
0000000
Display Data RAM
Normal Display
Inverse Display
Figure 7 Display Data RAM, Normal and Inverse Liquid Crystal Display Diagrams
Product Specification (V1.0) 12.28.2005
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