EM25LV512 Datasheet, PDF (10/30 Pages) ELAN Microelectronics Corp – 512 K (64K x 8) Bits Serial Flash Memory

EM25LV512
512 K (64K x 8) Bits Serial Flash Memory
SPECIFICATION
When the SRWD bit of the Status Register is set to “1,” two conditions need to be considered
according to the state with which Write Protect (W#) is in:
If Write Protect (W#) is driven High, it is allowed to write to the Status Register provided
that the Write enable Latch (WEL) bit has been previously set by a Write Enable (WREN)
instruction.
If Write Protect (W#) is driven Low, it is not allowed to write to the Status Register even if
the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction (attempts to write to the Status Register will be rejected and will not be
accepted for execution). Therefore, all data bytes in the memory area that are software
protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
Regardless of the order of the above two conditions, the Hardware Protected Mode (HPM)
can be entered by–
setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W#)
Low,
or
driving Write Protect (W#) Low after setting the Status Register Write Disable (SRWD)
bit.
The only way to exit from the Hardware Protected Mode (HPM) once it is entered, is to drive
Write Protect (W#) High. If Write Protect (W#) is permanently tied to High, the Hardware
Protected Mode (HPM) can never be activated. However, the Software Protected Mode
(SPM) can be activated by using the Block Protect (BP1, BP0) bits of the Status Register.
W# SRWD
Signal Bit
Mode
1
0
0
0 Software
Protected
1
1
(SPM)
Hardware
0
1 Protected
(HPM)
Write Protection of the
Status Register
Memory Content
Protected Area¹ Unprotected Area¹
Status Register is Writable (provided
that the WREN instruction has set the Protected against Page
WEL bit).
Program, Block Erase
The values in the SRWD, BP1 and and Chip Erase.
BP0 bits can be changed.
Ready to accept Page
Program, and Block
Erase instructions.
Status Register is Hardware write
protected. The values in the SRWD,
BP1 and BP0 bits cannot be
changed.
Protected against Page Ready to accept Page
Program, Block Erase Program, and Block
and Chip Erase.
Erase instructions.
Table 6: Protection Modes
This specification is subject to change without further notice. (11.08.2004 V1.0)
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