MC-4R128FKK8K Datasheet, PDF (9/13 Pages) Elpida Memory – 128MB 32-bit Direct Rambus DRAM RIMM Module

MC-4R128FKK8K
AC Electrical Specifications
Symbol
Parameter and Conditions^Note1
MIN.
TYP.
MAX.
Unit
ZL
Module Impedance of RSL signals
25.2
28.0
30.8
Ω
ZUL−CMOS
Module Impedance of SCK and CMD signals
23.8
28.0
TPD
∆TPD
∆TPD-CMOS
∆TPD- SCK,CMD
Average clock delay from finger to finger of all RSL clock
nets (CTM, CTMN,CFM, and CFMN) ^Note2
Propagation delay variation of RSL signals with respect to
TPD ^{Note1, 3}
Propagation delay variation of SCK signal with respect to
an average clock delay ^Note1
Propagation delay variation of CMD signal with respect to
SCK signal
−21
−250
−200
Vα/VIN
Attenuation Limit
VXF/VIN
VXB/VIN
Forward crosstalk coefficient
(300ps input rise time 20% - 80%)
Backward crosstalk coefficient
(300ps input rise time 20% - 80%)
RDC
DC Resistance Limit
32.2
Ω
0.89
ns
+21
ps
+250
ps
+200
ps
16.0
%
4.0
%
2.0
%
0.8
Ω
Notes 1. Specifications apply per channel.
2. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets
(CTM, CTMN, CFM, and CFMN).
3. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Adjusted ∆TPD Specification
Absolute
Symbol Parameter and conditions
Adjusted MIN./MAX.
MIN.
MAX.
Unit
∆TPD
Propagation delay variation of RSL signals with
respect to TPD
+/− [17+(18*N*∆Z0)] ^Note
−30
30
ps
Note N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 - MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
Preliminary Data Sheet E0252N10 (Ver. 1.0)
9