MC-4R128FKE6D-840 Datasheet, PDF (9/14 Pages) Elpida Memory – Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 16-BIT)

MC-4R128FKE6D-840
AC Electrical Specifications
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Parameter and Conditions
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Z
Module Impedance of RSL signals
   Ω
Module Impedance of SCK and CMD signals
  
TPD
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∆TPD
Propagation delay variation of RSL signals with respect to TPD ^Note1,2
−21
+21
ps
∆TPD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay ^Note1
∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal
−250
−200
+250 ps
+200 ps
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Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Adjusted ∆TPD Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN. MAX.
∆TPD Propagation delay variation of RSL signals with respect to TPD − >  1 ∆= @ ⁴⁹⁰ −30
+30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0 = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
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