EDJ2104BASE Datasheet, PDF (85/148 Pages) Elpida Memory – 2G bits DDR3 SDRAM

EDJ2104BASE, EDJ2108BASE
Additive Latency (MR1)
A posted /CAS read or write command when issued is held for the time of the Additive Latency (AL) before it is
issued inside the device. The read or write posted /CAS command may be issued with or without auto precharge.
The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL).
The value of AL is also added to compute the overall Write Latency (WL).
MRS (1) bits A4 and A3 are used to enable Additive latency.
MRS1
A4
A3
AL*
0
0
0
1
1
0
1
1
0 (posted CAS disabled)
CL − 1
CL − 2
Reserved
Note: AL has a value of CL − 1 or CL − 2 as per the CL value programmed in the /CAS latency MRS setting.
Preliminary Data Sheet E1505E20 (Ver. 2.0)
85