EDS2732AABJ-6B Datasheet, PDF (8/48 Pages) Elpida Memory – 256M bits SDRAM

EDS2732AABJ-6B
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4 V
input
2.0 V
I/O
0.4 V ^{0.8 V}
tT
tT
Output load
Relationship Between Frequency and Minimum Latency
E_Parameter
-6B
Frequency (MHz)
166
tCK (ns)
Symbol
6
O^{Active command to column command}
(same bank)
lRCD
3
Active command to active command
(same bank)
lRC
10
Active command to precharge command
(same bank)
lRAS
7
L _{Precharge command to active command}
(same bank)
lRP
3
Write recovery or data-in to precharge command
(same bank)
lDPL
2
Active command to active command
(different bank)
lRRD
2
P Self refresh exit time
lSREX
1
Last data in to active command
(Auto precharge, same bank)
lDAL
5
Self refresh exit to command input
lSEC
10
r _{Precharge command to high impedance}
(CL = 2)
lHZP
—
o ^{(CL = 3)}
lHZP
3
Last data out to active command
(Auto precharge, same bank)
lAPR
1
Last data out to precharge (early precharge)
(CL = 2)
lEP
—
d _{(CL = 3)}
lEP
–2
Column command to column command
lCCD
1
Write command to data in latency
lWCD
0
u _{DQM to data in}
lDID
0
DQM to data out
lDOD
2
CKE to CLK disable
c Register set to active command
/CS to command disable
t ^{Power down exit to command input}
lCLE
1
lMRD
2
lCDD
0
lPEC
1
CL
Unit
Notes
tCK
1
tCK
1
tCK
1
tCK
1
tCK
1
tCK
1
tCK
2
tCK
= [lDPL + lRP]
tCK
= [lRC]
3
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0507E40 (Ver. 4.0)
8