EDE1116ACSE-LI Datasheet, PDF (8/75 Pages) Elpida Memory – 1G bits DDR2 SDRAM WTR (Wide Temperature Range)

EDE1116ACSE-LI
Parameter
Symbol Grade max.
Unit Test condition
Operating current
(Bank interleaving)
IDD7
all bank interleaving reads, IOUT = 0mA; BL = 4,
CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
310
mA
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and /DQS. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
Parameter
5-5-5
CL (IDD)
5
tRCD (IDD)
15
tRC (IDD)
60
tRRD (IDD)
10
tFAW (IDD)
50
tCK (IDD)
3
tRAS (min.)(IDD)
45
tRAS (max.)(IDD)
70000
tRP (IDD)
15
tRFC (IDD)
127.5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDD7 Timing Patterns for 8 Banks
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
Speed bins
Timing Patterns
DDR2-667
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
Remark: A = Active. RA = Read with auto precharge. D = Deselect
Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using
a Burst length = 4.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0mA.
Data Sheet E1103E20 (Ver. 2.0)
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