EBE25UC8AAFV Datasheet, PDF (8/22 Pages) Elpida Memory – 256MB Unbuffered DDR2 SDRAM HYPER DIMM™

EBE25UC8AAFV
Block Diagram
/CS0
RS1
/DQS0
RS1
/DQS4
RS1
DQS0
RS1
DQS4
DM0
DQ0 to DQ7
RS1
8 RS1
DM ^{/CS DQS /DQS}
DQ0 ^D0
to DQ7
/DQS1
E DQS1
DM1
DQ8 to DQ15
RS1
RS1
RS1
8 RS1
/CS DQS /DQS
DM
DQ0 _D1
to DQ7
O _RS1
/DQS2
RS1
L^DQS2
DM4
DQ32 to DQ39
RS1
8 RS1
DM ^{/CS DQS /DQS}
DQ0 ^D4
to DQ7
/DQS5
DQS5
DM5
DQ40 to DQ47
RS1
RS1
RS1
8 RS1
/CS DQS /DQS
DM
D5 ^DQ0
to DQ7
RS1
/DQS6
RS1
DQS6
DM2
DQ16 to DQ23
/DQS3
DQS3
DM3
DQ24 to DQ31
BA0 to BA1
A0 to A12
/RAS
/CAS
/WE
CKE0
ODT0
VDDSPD
VREF
VDD
VSS
8
8
RS1
RS1
RS1
RS1
RS1
RS1
RS2
RS2
RS2
RS2
RS2
/CS DQS /DQS
DM
DQ0 _D2
to DQ7
P_{/CS DQS /DQS}
DM
DQ0 D3
r_{to DQ7}
DM6
DQ48 to DQ55
RS1
8 RS1
/CS DQS /DQS
DM
DQ0 _D6
to DQ7
/DQS7
DQS7
DM7
DQ56 to DQ63
RS1
RS1
RS1
8 RS1
/CS DQS ^/DQS
DM
DQ0 _D7
to DQ7
o _{BA0 to BA1: SDRAMs (D0 to D7)}
A0 to A12: SDRAMs (D0 to D7)
d ^{/RAS: SDRAMs (D0 to D7)}
/CAS: SDRAMs (D0 to D7)
/WE: SDRAMs (D0 to D7)
CKE: SDRAMs (D0 to D7)
u _{ODT:SDRAMs (D0 to D7)}
SPD
SDRAMs (D0 to D7)
c _{SDRAMs (D0 to D7)}
t ^{SDRAMs (D0 to D7)}
Serial PD
SCL
SCL
SDA
SDA
SA0
A0 _U0
SA1
A1
SA2
A2 WP
Notes :
1. DQ wiring maybe changed within a byte.
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be meintained as shown.
3. Refer to the appropriate clock wiring topology
under the DIMM wiring details section of this document.
* D0 to D7 : 256M bits DDR2 SDRAM
U0 : 2k bits EEPROM
Rs1 : 22Ω
Rs2 : 5.1Ω
Preliminary Data Sheet E0527E12 (Ver. 1.2)
8