EDJ1104BFSE Datasheet, PDF (73/147 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1104BFSE, EDJ1108BFSE
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
tCKSRX _{max. (10 ns; 5tCK)}
/RESET
200ms
500ms
10ns
tIS
CKE
Command
BA
tXPR^*2
tIS
tMRD
tMRD
tMRD
tDLLK
tMOD
*¹
MRS MRS MRS MRS ZQcal
MR2
tIS
MR3
MR1
MR0
tZQinit
ODT
DRAM_RTT
Notes: 1. From time point "Td" until "Tk", NOP or DESL commands must be
applied between MRS and ZQcal commands.
2. tXPR = max. (tXS; 5tCK)
Reset and Initialization Sequence at Power-On Ramping
: VIH or VIL
Reset and Initialization with Stable Power
The following sequence is required for /RESET at no power interruption initialization.
1. Assert /RESET below 0.2 × VDD anytime when reset is needed (all other inputs may be undefined). /RESET
needs to be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time
10ns).
2. Follow Power-Up Initialization Sequence steps 2 to 11.
3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
/RESET
CKE
Command
BA
tCKSRX _{max. (10 ns; 5tCK)}
100ns
500ms
tIS
10ns
tXPR^*2
tIS
tMRD
tMRD
tMRD
tDLLK
tMOD
tZQinit
*¹
MRS
MR2
tIS
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
ODT
DRAM_RTT
Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be
applied between MRS and ZQCL commands.
2. tXPR = max. (tXS; 5tCK)
Reset Procedure at Power Stable Condition
: VIH or VIL
Preliminary Data Sheet E1653E20 (Ver. 2.0)
73