HM5164805F Datasheet, PDF (7/34 Pages) Hitachi Semiconductor – 64 MEDO DRAM (8-Mword X 8-bit) 8 k Refresh/4 k Refresh

HM5164805F Series, HM5165805F Series
Operation Table
RAS
H
L
L
L
L
L
H to L
CAS
×
L
L
L
L
H
L
WE
×
H
L*²
L*²
H to L
×
H
OE
×
L
×
H
L to H
×
×
I/O 0 to I/O 7
High-Z
Dout
Din
Din
Dout/Din
High-Z
High-Z
L
L
H
H
High-Z
Notes: 1. H: V_IH (inactive), L: V_IL (active), ×: V_IH or V_IL
2. t_WCS ≥ 0 ns: Early write cycle
t_WCS < 0 ns: Delayed write cycle
Operation
Standby
Read cycle
Early write cycle
Delayed write cycle
Read-modify-write cycle
RAS-only refresh cycle
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
Read cycle (Output disabled)
Absolute Maximum Ratings
Parameter
Symbol
Terminal voltage on any pin relative to V_SS V_T
Power supply voltage relative to V_SS
V_CC
Short circuit output current
Iout
Power dissipation
P_T
Storage temperature
Tstg
Value
Unit
–0.5 to V_CC + 0.5 (≤ 4.6 V (max)) V
–0.5 to +4.6
V
50
mA
1.0
W
–55 to +125
°C
DC Operating Conditions
Parameter
Symbol Min
Typ
Max
Unit
Notes
Supply voltage
Input high voltage
Input low voltage
Ambient temperature range
V_CC
3.0
3.3
3.6
V
1, 2
V_SS
0
0
0
V
2
V_IH
2.0
—
V_CC + 0.3 V
1
V_IL
–0.3
—
0.8
V
1
Ta
0
—
70
˚C
Notes: 1. All voltage referred to V_SS.
2. The supply voltage with all V_CC pins must be on the same level. The supply voltage with all V_SS pins
must be on the same level.
Data Sheet E0098H10
7