MC-45D32DA721 Datasheet, PDF (6/16 Pages) Elpida Memory – 32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
(ACT-PRE)
Symbol
Test condition
/CAS Grade
latency
IDD0 t^RC = t^RC(MIN.), t^CK = t^{CK (MIN.)}, One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
-C75
-C80
MIN.
MAX.
TBD
Unit Notes
mA
TBD
Operating current
(ACT-READ-PRE)
IDD1 t^RC = t^RC(MIN.), t^CK = t^{CK (MIN.)}, One CL = 2 -C75
bank, Active-read-precharge,
IO = 0 mA, Burst length = 2,
Address and control inputs
-C80
CL = 2.5 -C75
changing once per clock cycle
-C80
Precharge power down
standby current
IDD2P CKE ≤ V^IL(MAX.), t^CK = t^CK(MIN.),
All banks idle, Power down mode
Idle standby current
IDD2N
CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All banks idle, Address and other control inputs
changing once per clock cycle
Active power down
standby current
IDD3P CKE ≤ V^IL(MAX.), t^CK = t^CK(MIN.), One bank active,
Power down mode
Active standby current
IDD3N
/CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =
tRAS(MAX.), One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
Operating current
(Burst read)
IDD4R
tCK = tCK(MIN.), Continuous burst
read, Burst length = 2, IO =
0mA, One bank active,
Address and control inputs
changing once per clock cycle
CL = 2 -C75
-C80
CL = 2.5 -C75
-C80
Operating current
(Burst write)
IDD4W
tCK = tCK(MIN.), Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
CL = 2 -C75
-C80
CL = 2.5 -C75
-C80
CBR (auto) refresh current IDD5 t^RFC = t^RFC(MIN.)
-C75
-C80
Self refresh current
IDD6 CKE ≤ 0.2 V
TBD
TBD
TBD
TBD
TBD
TBD
mA 1
mA
mA
TBD
mA
TBD
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA 2
mA ₂
mA
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
Input leakage current
II(L) VI = 0 to 3.6 V, all other pins not under test = 0 V
TBD
Output leakage current
IO(L) DOUT is disabled, VO = 0 to VDDQ + 0.3 V
TBD
Output high current
Output low current
IOH VOUT = VDDQ − 0.43 V
IOL VOUT = 0.35 V
TBD
TBD
MAX.
TBD
TBD
Unit Notes
µA
µA
mA
mA
6
Preliminary Data Sheet E0037N10