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EBE51UD8AGWA Datasheet, PDF (6/25 Pages) Elpida Memory – 512MB Unbuffered DDR2 SDRAM DIMM
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EBE51UD8AGWA
Byte No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
Minimum active to precharge time
(tRAS)
-6E, -5C
0 0 1 0 1 1 0 1 2DH
Module rank density
1 0 0 0 0 0 0 0 80H
Address and command setup time
before clock (tIS)
-6E
0 0 1 0 0 0 0 0 20H
-5C
0 0 1 0 0 1 0 1 25H
Address and command hold time after
clock (tIH)
0 0 1 0 0 1 1 1 27H
-6E
-5C
0 0 1 1 0 1 1 1 37H
Data input setup time before clock
(tDS)
-6E, -5C
0 0 0 1 0 0 0 0 10H
Data input hold time after clock (tDH)
-6E
0
0
0
1
0
1
1
1
17H
-5C
0 0 1 0 0 0 1 0 22H
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
Internal write to read command delay
(tWTR)
0 0 0 1 1 1 1 0 1EH
-6E, -5C
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
7.5ns
15ns
45ns
512M bytes
0.20ns*1
0.25ns*1
0.27ns*1
0.37ns*1
0.10ns*1
0.17ns*1
0.22ns*1
15ns*1
7.5ns*1
7.5ns*1
TBD
Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
-6E, -5C
0 0 1 1 1 1 0 0 3CH
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
0
1
0
0
1
69H
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
Dout to DQS skew
-6E
0 0 0 1 1 0 0 0 18H
-5C
0 0 0 1 1 1 1 0 1EH
Data hold skew (tQHS)
-6E
0 0 1 0 0 0 1 0 22H
-5C
0 0 1 0 1 0 0 0 28H
Undefined
60ns*1
105ns*1
8ns*1
0.24ns*1
0.30ns*1
0.34ns*1
0.40ns*1
Preliminary Data Sheet E0921E10 (Ver. 1.0)
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